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<div class="header">
  <div class="headertitle"><div class="title">MDMA_Channel_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s___device.html">CMSIS_Device</a> &raquo; <a class="el" href="group__stm32h723xx.html">Stm32h723xx</a> &raquo; <a class="el" href="group___peripheral__registers__structures.html">Peripheral_registers_structures</a></div></div></div>
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<tr class="heading"><td colspan="2"><h2 id="header-pub-attribs" class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Public Attributes</h2></td></tr>
<tr class="memitem:a5a5efbf83f104427b927e6b207cf26d1" id="r_a5a5efbf83f104427b927e6b207cf26d1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a5a5efbf83f104427b927e6b207cf26d1">CISR</a></td></tr>
<tr class="memitem:a33065aa1d54e1aba74570382f7e367d4" id="r_a33065aa1d54e1aba74570382f7e367d4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a33065aa1d54e1aba74570382f7e367d4">CIFCR</a></td></tr>
<tr class="memitem:a9811369e1b621b63eff14f3a50986062" id="r_a9811369e1b621b63eff14f3a50986062"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9811369e1b621b63eff14f3a50986062">CESR</a></td></tr>
<tr class="memitem:a835c47def48257f36879ad0ff5e3bb8e" id="r_a835c47def48257f36879ad0ff5e3bb8e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a835c47def48257f36879ad0ff5e3bb8e">CCR</a></td></tr>
<tr class="memitem:a17b5ca2bff81a3b7ffffd4b3471973ae" id="r_a17b5ca2bff81a3b7ffffd4b3471973ae"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a17b5ca2bff81a3b7ffffd4b3471973ae">CTCR</a></td></tr>
<tr class="memitem:ad27a6cee3f90bb9221cc993a6d4c10c3" id="r_ad27a6cee3f90bb9221cc993a6d4c10c3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad27a6cee3f90bb9221cc993a6d4c10c3">CBNDTR</a></td></tr>
<tr class="memitem:a9b845a89d1c4dec3e6df2d443955c0d8" id="r_a9b845a89d1c4dec3e6df2d443955c0d8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a9b845a89d1c4dec3e6df2d443955c0d8">CSAR</a></td></tr>
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<tr class="memitem:a94503b7dc3f8d03923ecf4376b5956a9" id="r_a94503b7dc3f8d03923ecf4376b5956a9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a94503b7dc3f8d03923ecf4376b5956a9">CBRUR</a></td></tr>
<tr class="memitem:a5b6aba31216cd09145878456e935262d" id="r_a5b6aba31216cd09145878456e935262d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a5b6aba31216cd09145878456e935262d">CLAR</a></td></tr>
<tr class="memitem:a68b30850de97b936637d53508be9fdf2" id="r_a68b30850de97b936637d53508be9fdf2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a68b30850de97b936637d53508be9fdf2">CTBR</a></td></tr>
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<a name="doc-variable-members" id="doc-variable-members"></a><h2 id="header-doc-variable-members" class="groupheader">Member Data Documentation</h2>
<a id="ad27a6cee3f90bb9221cc993a6d4c10c3" name="ad27a6cee3f90bb9221cc993a6d4c10c3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ad27a6cee3f90bb9221cc993a6d4c10c3">&#9670;&#160;</a></span>CBNDTR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MDMA_Channel_TypeDef::CBNDTR</td>
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<p>MDMA Channel x block number of data register, Address offset: 0x54 </p>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MDMA_Channel_TypeDef::CBRUR</td>
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<p>MDMA channel x Block Repeat address Update register, Address offset: 0x60 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a835c47def48257f36879ad0ff5e3bb8e">&#9670;&#160;</a></span>CCR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MDMA_Channel_TypeDef::CCR</td>
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<p>MDMA channel x control register, Address offset: 0x4C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aa79c99d83c06c265c094b0e2bb462993">&#9670;&#160;</a></span>CDAR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MDMA_Channel_TypeDef::CDAR</td>
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<p>MDMA channel x destination address register, Address offset: 0x5C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a9811369e1b621b63eff14f3a50986062">&#9670;&#160;</a></span>CESR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MDMA_Channel_TypeDef::CESR</td>
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<p>MDMA Channel x error status register, Address offset: 0x48 </p>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MDMA_Channel_TypeDef::CIFCR</td>
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<p>MDMA channel x interrupt flag clear register, Address offset: 0x44 </p>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MDMA_Channel_TypeDef::CISR</td>
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<p>MDMA channel x interrupt/status register, Address offset: 0x40 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a5b6aba31216cd09145878456e935262d">&#9670;&#160;</a></span>CLAR</h2>

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<p>MDMA channel x Link Address register, Address offset: 0x64 </p>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MDMA_Channel_TypeDef::CMAR</td>
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<p>MDMA channel x Mask address register, Address offset: 0x70 </p>

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<p>MDMA channel x Mask Data register, Address offset: 0x74 </p>

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<p>MDMA channel x source address register, Address offset: 0x58 </p>

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<p>MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 </p>

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<p>MDMA channel x Transfer Configuration register, Address offset: 0x50 </p>

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<p>Reserved, 0x6C </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/CMSIS/Device/ST/STM32H7xx/Include/<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a></li>
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